To improve performances of ultralarge-scale integrated (ULSI) semiconductor circuits, it is inevitable to enhance the performance of field effect transistors (FETs), which are major constituent elements of ULSI chips. Until today, development of such high-performance FETs has been advanced mainly by miniaturization techniques. However, in recent years, critical limits of the miniaturization are reported. One of the limits is an increase in parasitic resistance of electrodes at source/drain regions, as suggested in S. D. Kim et al., “Advanced model and analysis for series resistance in sub-100 nm CMOS including poly-deposition and overlap doping gradient effect,” International Electrical and Devices Meeting (IEDM), Tech. Digest, No. 31.3 (2000).
The parasitic resistance typically includes two major elements: the electrical resistance of an electrode per se, and the contact resistance between the electrode and its underlying semiconductor substrate. Even when the resistance of channel part is reduced by downscaling of FETs, if the electrode's parasitic resistance remains unable to be reduced, device performance enhancement is hardly attainable. In the existing metal oxide semiconductor FETs (MOSFETs), one major approach is to employ nickel silicide (NiSi) as the material for source/drain electrodes. However, to achieve further miniaturization of MOSFETs, a need is felt to reduce the parasitic resistance more strictly than the case of NiSi electrodes.
Recently, in order to further reduce the electrode contact resistance to an extent lower than that of NiSi electrodes, a technique has been proposed for using different kinds of metal silicides for the electrodes between n-type FETs and p-type FETs. This is known as the “dual silicide.” With this technique, metal silicide that is large in work function is used for p-type FETs whereas metal silicide less in work function is for n-type FETs.
Using this dual-silicide design makes it possible to lower the level of Schottky barrier against holes and electrons between a metal silicide electrode and a diffusion layer (semiconductor substrate), thereby to reduce the contact resistance. Recent studies reveal that one preferable example of the large work function metal silicide for use in p-type FETs is a silicide of noble metals whereas an example of the low work function metal silicide for use in n-type FETs is a silicide of rare earth metals.
Unfortunately, even when the contact resistance is reduced by the separate use of such different metal silicides between p- and n-type FETs, the resultant device is still faced with the risk of performance degradation occurring due to the fact that the resistance of an electrode per se to be determined by its metallic material can increase to become greater than that of NiSi electrodes. An approach to avoiding this is to employ a technique as disclosed in JP-A-2005-123626(KOKAI), for forming a noncontiguous metal cluster in the interface between a layer of metal silicide that is low in its own resistance and a diffusion layer associated therewith. This technique is the one that utilizes what is called the Kirkendall effect: atoms of respective constituent elements in an alloy behave to diffuse at different speeds. It has been reported that with this technique, the noncontiguous metal cluster of the interface is optimizable in its metal work function, thereby making it possible to attain the conflicting goals—i.e., reducing the contact resistance of an electrode and reducing the resistance of such electrode per se.
Nevertheless, in the technique as taught by JP-A-2005-123626(KOKAI), it is a must to design a device structure with mixed presence of a metal cluster and a metal silicide of electrode at the interface. This is inevitable to perform the Kirkendall effect-used fabrication process successfully. Also inevitably, metallic material used for the metal cluster is restricted to a specific kind of metal that is hardly silicidable. Due to the presence of these penalties, the advantages of the prior known approaches do not come without accompanying a problem which follows: it is difficult to sufficiently lower the Schottky barrier, which leads to unavoidable difficulty in sufficient reduction of the electrode contact resistance.